This patent application is related to simultaneously filed patent applications titled: LOGICAL DATA BLOCK, MAGNETIC RANDOM ACCESS MEMORY, MEMORY MODULE, COMPUTER SYSTEM AND METHOD, and METHOD FOR ADAPTIVELY WRITING A MAGNETIC RANDOM ACCESS MEMORY, both copending.
A magnetic memory such as a MRAM typically includes an array of magnetic memory cells. A typical magnetic memory cell includes a layer of magnetic film in which magnetization is alterable and a layer of magnetic film in which magnetization is fixed or xe2x80x9cpinnedxe2x80x9d in a particular direction. The magnetic film having alterable magnetization may be referred to as a data storage layer. The magnetic film that is pinned may be referred to as a reference layer.
The orientation of magnetization of each magnetic memory cell may assume one of two stable orientations at any given time. These two stable orientations are referred to as xe2x80x9cparallelxe2x80x9d and xe2x80x9canti-parallelxe2x80x9d, and represent logic states of xe2x80x9c1xe2x80x9d and xe2x80x9c0,xe2x80x9d respectively. FIGS. 1A and 1B illustrate the basic structure of a conventional magnetic memory cell 100 having a reference layer 102 with a same-axis orientation of magnetization with respect to the easy-axis of the data storage layer 104. The magnetic memory cell 100 includes a tunnel barrier 106 between the data storage layer 104 and the reference layer 102. This structure of the magnetic memory cell 100 may be referred to as a spin tunneling device (STD) in that electrical charge migrates through the tunnel barrier 106 during read operations. This electrical charge migration through the tunnel barrier 106 is due to a phenomenon known as spin tunneling and occurs when a read voltage is applied to the magnetic memory cell 100.
FIG. 1A illustrates a magnetic memory cell 100 having a data storage layer 104 with parallel magnetic orientation relative to the reference layer 102. Vector M1 represents the overall or resulting orientation of magnetization in the data storage layer 104. Vector M1 includes contributions from magnetizations along the easy-axis and in the edge domains of the data storage layer 104. The orientation of magnetization in the reference layer 102 is represented by a vector M2 that is fixed in a direction parallel to the easy-axis of the data storage layer 104. Thus, FIG. 1A is representative of a magnetic memory cell storing a logical xe2x80x9c1xe2x80x9d state.
Vector M1 may be changed depending upon the logic state of the magnetic memory cell 100. Vector M1 is manipulated by the application of magnetic fields using conductors associated with the magnetic memory cell 100. These magnetic fields are applied to flip or reverse the directions of the magnetizations, vector M1, in the data storage layer 104 including the easy-axis magnetization and the edge domains. FIG. 1B illustrates a magnetic memory cell 100 having a reference layer 102 with anti-parallel magnetic orientation relative to the reference layer 102. Thus, FIG. 1B is representative of a magnetic memory cell storing a logical xe2x80x9c0xe2x80x9d state.
The logic state of a magnetic memory cell may be indicated by its resistance, which depends on the relative orientations of magnetization in its data storage and reference layers. Such a magnetic memory cell is typically in a low resistance state if the orientation of magnetization in its data storage layer is substantially parallel to the orientation of magnetization in its reference layer. In contrast, a magnetic memory cell is typically in a high resistance state if the orientation of magnetization in its data storage layer is substantially anti-parallel to the orientation of magnetization in its reference layer.
A magnetic memory cell may be written to a desired logic state by applying magnetic fields that rotate the orientation of magnetization in its data storage layer. Typically, the orientation of magnetization in the data storage layer aligns along an axis of the data storage layer that is commonly referred to as an xe2x80x9ceasy-axis.xe2x80x9d The magnetic fields may be applied to flip the orientation of magnetization in the data storage layer along its easy-axis to either a parallel or anti-parallel orientation with respect to the orientation of magnetization in the reference layer depending on the desired logic state.
Prior magnetic memories typically include an array of word lines and bit lines that are used to apply magnetic fields to the magnetic memory cells during writing. The magnetic memory cells are usually located at intersections of the word lines and bit lines. A selected magnetic memory cell may be written by applying electrical currents to the particular word and bit lines that intersect at the selected magnetic memory cell. Typically, an electrical current applied to the particular bit line generates a magnetic field substantially aligned along the easy-axis of the selected magnetic memory cell. The magnetic field aligned to the easy-axis may be referred to as a longitudinal write field. An electrical current applied to the particular word line usually generates a magnetic field substantially perpendicular to the easy-axis of the selected magnetic memory cell.
Typically, only the selected magnetic memory cell receives both the longitudinal and the perpendicular write fields. Other magnetic memory cells coupled to the particular word line usually receive only the perpendicular write field. Other magnetic memory cells coupled to the particular bit line usually receive only the longitudinal write field.
The magnitudes of the longitudinal and the perpendicular write fields are usually chosen to be high enough so that the selected magnetic memory cell switches its logic state, but low enough so that the other magnetic memory cells which are subject to either the longitudinal or the perpendicular write field do not switch. An undesirable switching of a magnetic memory cell that receives only the longitudinal or the perpendicular write field is commonly referred to as xe2x80x9chalf-selectxe2x80x9d switching.
Manufacturing variation among the magnetic memory cells may increase the likelihood of half-select switching. For example, manufacturing variation in the longitudinal or perpendicular dimensions or shapes of the magnetic memory cells may increase the likelihood of half-select switching. In addition, variation in the thicknesses or the crystalline anisotropy of data storage layers may increase the likelihood of half-select switching. Unfortunately, such manufacturing variation decreases the yield in manufacturing processes for magnetic memories and reduces the reliability of prior magnetic memories.
The reference layer of a magnetic memory cell is usually a layer of magnetic material in which magnetization is fixed or xe2x80x9cpinnedxe2x80x9d in a particular direction. In a conventional magnetic memory cell, the reference layer may be formed with its magnetization pinned in a direction that is parallel to the easy-axis of the data storage layer. As a consequence, the orientation of magnetization in the reference layer of the conventional magnetic memory cell is typically parallel to the easy-axis of the data storage layer.
A conventional magnetic memory cell may be written by applying magnetic fields that reverse the orientation of magnetization in the data storage layer from one direction to the other along its easy-axis. This reversal causes the magnetic memory cell to switch between its high and low resistance states. The logic state of the magnetic memory cell may be determined during a read operation by measuring its resistance.
Typically, the data storage layer is fabricated as a rectangle or oval with an elongated dimension along its easy-axis. These configurations minimize the negative effects of edge domains. Such a structure usually increases easy-axis contribution to the resulting orientation of magnetization in the data storage layer in comparison to contributions from the edge domains. The rectangular or oval configuration sets the shape anisotropy for the bit cell and provides a bi-stable structure. The parallel state requires more energy to flip the orientation of magnetization in the data storage layer during write operations.
Further, the memory cells are aligned so that the easy axes are parallel with their respective word lines. One problem with this configuration is that during a write operation, the memory cells not actually being written, but which share the same bit line, are in a half-select mode. During half-select, a write current can generate a magnetic field sufficient enough for certain susceptible bits to cause the magnetic orientation of data storage layer to reverse from a parallel orientation to a low-energy state or anti-parallel orientation. If the orientation was originally in a parallel orientation and then is flipped to be anti-parallel, an error will have occurred. Error correction techniques may correct some of these occurrences, but when the occurrences exceed the ability of the error correction techniques, uncorrectable errors will result. This same form of half-select error can occur during a read operation where the word line is held to a given potential value, typically ground, and a sense or read potential is applied to all of the columns. While the generated read current for a given bit is typically small (on the order of 1 xcexcA or less) and all of the bits on a selected row have this same current flow out the row, the net current can be enough to half-select those memory cells sharing the word line if the word line is oriented to generate easy-axis field, even though they are not presently being read.
Further, as the dimensions of the memory cells continue to decrease, their susceptibility to half-select-induced errors increases. Accordingly, there exists a need in the art for a method, apparatus and system for reducing half-select errors.
A method of erasing a logical data block of a MRAM according to an embodiment of the present invention is disclosed. The method comprises providing a MRAM having a logical data block configured for a distribution of selected and unselected write field thresholds when switching from a logical one state to a logical zero state, wherein the selected write field threshold is separated from the unselected write field threshold by a preselected amount and writing all bits of the logical data block to the logical zero state.
Additional features and advantages of the invention will be apparent from the detailed description which follows, taken in conjunction with the accompanying drawings, which together illustrate, by way of example, features of embodiments of the present invention.